High density memory structure

ABSTRACT

A dynamic random access memory (DRAM) integrated circuit ( 10 ). The DRAM ( 10 ) includes a recessed region ( 20 ) defined in a semiconductor substrate ( 22 ). This recessed region has substantially vertical sides ( 34 ) extending from a bottom surface ( 32 ). A field effect transistor ( 18 ) is defined adjacent to the recessed region ( 20 ). A capacitor structure, including a lower capacitor plate ( 26 ), a capacitor dielectric ( 28 ), and an upper capacitor plate ( 30 ), is defined in the recessed region ( 20 ) and over the field effect transistor ( 18 ), thereby providing a greater capacitor surface.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional patent application of U.S. Ser.No. 08/598,258 filed Feb. 7, 1996 which is a nonprovisional applicationof U.S. provisional patent application Ser. No. 60/001,810, filed Aug.4, 1995.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to the manufacture of semiconductorintegrated circuits. More particularly, the invention is illustratedwith regard to memory cell structures for a dynamic random access memory(DRAM) device, but it will be recognized that the invention has a widerrange of applicability. Merely by way of example, the invention may beapplied in the manufacture of other semiconductor devices such asapplication specific integrated circuits (ASICs), microprocessors(MICROs), other memory devices, and the like.

[0003] In the fabrication of DRAM devices, memory storage capacity ofeach DRAM cell has long been a problem. In a DRAM cell, storage capacityis the greatest amount of electrical charge that can be stored in adielectric material between a lower capacitor electrode and an uppercapacitor electrode. This storage capacity is proportional to thesurface area of the capacitor dielectric between these capacitorelectrodes. Accordingly, a larger capacitor surface area corresponds toincreased storage capacity.

[0004] Lower density DRAM cells used in 256 kbit DRAM designs reliedupon planar capacitor structures, which were built roughly in the samehorizontal spatial plane as the transistor gate electrodes. Thesecapacitor structures were formed overlying transistor source/drainregions in the limited spatial region between the transistor gateelectrode and the field oxide isolation region. These planar capacitorstructures were effective in providing enough storage capacity for theselower density DRAM cells. As DRAM cell sizes became smaller for higherdensity devices, however, it was increasingly difficult to design acapacitor structure with enough storage capacity within this smallercell size.

[0005] One technique used to improve memory storage capacity for thesehigher density DRAM cells is a stack capacitor. The stack capacitorforms its capacitor structure “over” the gate electrode of the fieldeffect transistor, rather than being in the same spatial plane as thegate electrode. Therefore, the stack capacitor increases its capacitorsurface area by fabrication of the capacitor structure over the gateelectrode. A limitation with this capacitor type is, however, difficultyin processing. In fact, the stack capacitor creates a DRAM cellstructure with an extremely complicated topography. This extremelycomplicated topography creates difficult fabrication techniques,rendering longer fabrication turn-around-times, lower device yields, andhigher device costs.

[0006] Another technique proposed to improve memory storage capacity forhigher density DRAM cells is a trench capacitor. The trench capacitorforms its structure within a recessed region or “trench” in the wellregion of the DRAM cell. This trench is defined by a selected width anddepth. The trench also includes a trench side, defining the lowercapacitor electrode. Overlying the trench side is the capacitordielectric layer. A conductive fill material overlying this capacitordielectric layer defines the upper capacitor electrode. Increasedcapacitor storage occurs with a greater capacitor surface area.

[0007] Greater capacitor surface area correlates to a trench design thatis spatially deeper or wider. The trench width can not be substantiallyenlarged due to the limited amount of substrate surface area for eachmemory cell. Thus, the trench must be enlarged by fabrication of thedeeper trench. This deeper trench, however, is often difficult tofabricate accurately due to its high aspect ratio. Another limitation isthe possible presence of “soft error” problems due to the relativelylarge junction area associated with this trench design. A furtherlimitation is sidewall doping used for the lower capacitor electrodeoften affects the quality of the capacitor dielectric layer.

[0008] From the above it is seen that a high density memory cellstructure that is easy to fabricate, cost effective, and reliable isoften desired.

SUMMARY OF THE INVENTION

[0009] The present invention provides a technique, including a methodand structure, for an improved capacitor for a DRAM integrated circuitdevice. This improved capacitor is provided with a larger surface areawithout the formation of deeper trenches.

[0010] In a specific embodiment, the present invention provides adynamic random access memory (DRAM) integrated circuit. This DRAMintegrated circuit includes a semiconductor substrate comprising arecessed region. The recessed region has vertical sides extending from abottom surface. A field effect transistor, including a source/drainregion, is provided adjacent to the recessed region. The DRAM integratedcircuit also includes an insulating layer overlying the recessed region.A lower capacitor plate overlying the insulating layer and over aportion of the field effect transistor is also provided. This lowercapacitor plate is connected to the source/drain region. The DRAMintegrated circuit further includes a capacitor dielectric overlying thelower capacitor plate, and an upper capacitor plate overlying thedielectric layer. The lower capacitor plate, capacitor dielectric, andupper capacitor plate define the capacitor structure.

[0011] In an alternative embodiment, a method of forming a capacitorstructure for a dynamic random access memory integrated circuit elementis provided. This method includes providing a semiconductor substrate,and forming a recessed region in the substrate. This recessed region hasvertical sides extending from a bottom surface. The method also includesforming an insulating layer defined overlying the recessed region. Afurther step of forming a source/drain region adjacent to the recessedregion is provided. The method includes forming a lower capacitor plateoverlying the insulating layer and over a portion of the field effecttransistor. This lower capacitor plate is connected to the source/drainregion. The method also includes forming a capacitor dielectricoverlying the lower capacitor plate, and forming an upper capacitorplate overlying the dielectric layer. The lower capacitor plate,capacitor dielectric, and upper capacitor plate define the capacitorstructure.

[0012] A further alternative embodiment includes a bit-line structurefor a dynamic random access memory integrated circuit. This bit-linestructure includes a semiconductor substrate comprising a recessedregion. This recessed region has vertical sides extending from a bottomsurface. A field effect transistor is defined adjacent to the recessedregion. An insulating layer is defined overlying the recessed region,and a conductor is defined within the recessed region. This conductorconnects to the source/drain region, and defines a bit-line.

[0013] An alternative specific embodiment includes a method of forming abit-line structure in a dynamic random access memory integrated circuit.This method includes providing a semiconductor substrate, and forming arecessed region in the semiconductor substrate. This recessed region hasvertical sides extending from a bottom surface. The method also includesa step of forming an insulating layer defined overlying the recessedregion, and forming a field effect transistor adjacent to the recessedregion. A conductor is defined within the recessed region. Thisconductor connects to the source/drain region, and defines a bit-line.

[0014] The present invention achieves these benefits in the context ofknown process technology. However, a further understanding of the natureand advantages of the present invention may be realized by reference tothe latter portions of the specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a simplified cross-sectional view diagram of a DRAMintegrated circuit device according to the present invention;

[0016]FIG. 2 is a simplified cross-sectional view diagram of a bit-linestructure for the DRAM of FIG. 1;

[0017]FIG. 3 is an alternative cross-sectional view diagram of thebit-line structure of FIG. 2;

[0018]FIG. 4 is a simplified top-view diagram of the DRAM of FIG. 1; and

[0019] FIGS. 5-14 illustrate a simplified fabrication method of a DRAMintegrated circuit device according to the present invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENT I. Dram Device Structures

[0020]FIG. 1 is a simplified cross-sectional view diagram of a DRAMintegrated circuit device 10, according to the present invention. Thepresent device is merely an illustration and should not limit the scopeof the claims as defined herein. Generally, the DRAM device 10 includesa plurality of memory cell regions 12, an overlying dielectric layer 14,a top metallization layer 16, a passivation layer 17, and otherelements. The memory cell regions can be fabricated using conventionalCMOS processing techniques or the like.

[0021] Each memory cell region 12 is defined within a P-type well region22. A field effect transistor 18 is defined within this P-type wellregion 22. The field effect transistor is an N-type channel metal oxidesemiconductor (MOS) device, including a gate electrode 54. The gateelectrode 54, termed as the word line, overlies a thin gate dielectriclayer(s) 52. Sidewalls 56 are defined adjacent to sides of the gateelectrode 54. Overlying the gate electrode 54 is a cap oxide layer 58.An inter-layer dielectric 60 is formed overlying the cap oxide layer 58and also is formed overlying portions of source/drain regions 38, 46.Each source/drain region includes an N− type LDD region 42, 48 and an N+type source/drain region 40, 50. As shown, N+ type source/drain region40 is connected to a trench capacitor 20, also defined within the P-typewell region 22.

[0022] This trench capacitor serves as a memory storage device forstoring electrical charge in a capacitor dielectric 28 between a lowercapacitor plate 26 and an upper capacitor plate 28. This capacitordielectric can be any suitable insulating material such as silicondioxide, silicon nitride, and others. Preferably, the capacitordielectric is a sandwiched layer comprising silicon dioxide, siliconnitride, and silicon dioxide, known as oxide-on-nitride-on-oxide (ONO).Of course, other combinations of dielectric materials also can be useddepending upon the application.

[0023] The lower capacitor plate 26 is defined over the field effecttransistor 18 and is defined overlying an insulating layer 24, overlyingthe trench bottom 32 and sides 34. This insulating layer is at aselected thickness sufficient for isolating the P-type well region fromthe lower capacitor plate 26. A high quality silicon dioxide materialcan be used as this insulating layer for isolation purposes. The layer,however, is removed from an upper portion 36 of the trench sides 34,providing an electrical contact between the lower capacitor plate 26 andthe N+ type source/drain region 40.

[0024] The lower capacitor plate can be any suitable conductive layer.Preferably, the lower capacitor plate is a polysilicon layer in-situdoped using N-type impurities, e.g., phosphorous, etc. The lowercapacitor plate can also be made from a sandwiched structure, includingmulti-metal layers, suicides, combinations thereof, and the like. Inanother embodiment, the lower capacitor plate is made using a texturedor rough polysilicon layer. This textured polysilicon layer, unlikesmooth polysilicon, has small ridges, thereby increasing the effectivesurface area of the capacitor. As shown, the lower capacitor plateextends from the insulating layer on the trench bottom 32, overlies theinsulating layer on the trench sides 34, contacts the source/drainregion 40, and extends over the inter-layer dielectric 60, overlying thefield effect transistor 18.

[0025] The upper capacitor plate 28 is defined overlying the capacitordielectric 28. This upper capacitor plate extends from the trenchinsulating layer bottom 32 and extends overlying the capacitordielectric layer, which overlies the lower capacitor plate. Preferably,the upper capacitor plate also is made from an in-situ doped polysiliconmaterial using N-type impurities. Alternatively, the upper capacitorplate can also be made from a sandwiched structure, includingmulti-metal layers, silicides, combinations thereof, and the like.Another embodiment uses an upper capacitor plate made of a textured orrough polysilicon layer. This textured polysilicon layer, unlike smoothpolysilicon, has small ridges, thereby increasing the effective surfacearea of the capacitor.

[0026] As can be seen, the present trench capacitor structure, includingthe lower capacitor plate 26, the capacitor dielectric 28, and the uppercapacitor plate 30, extends from the trench bottom 32, extends along itssides 34, and extends over the field effect transistor 18. Accordingly,this trench capacitor structure can be made substantially longer thanthe conventional capacitor structures.

[0027] The present trench capacitor is designed to provide increasedcapacitance without the undesirable characteristics of the conventionaltrench structure, which is often difficult to fabricate consistentlybeyond a certain depth. Using a 0.25 μm design rule, as an example, thetrench depth ranges from about 8,000 to about 12,000 Å, and preferablyabout 10,000 Å. The trench also includes a 2,500 Å width for bit-lineand isolation area. The trench width for the capacitor is around the4,000 Å range. This trench structure provides a lower capacitor plate.The thicknesses of this capacitor plate ranges from about 1,000 to about1,400 Å, and preferably about 1,200 Å. As noted, a portion of the lowercapacitor plate is defined overlying the field effect transistor as wellas the trench side.

[0028]FIG. 2 is a simplified cross-sectional view diagram 200 of abit-line structure for the DRAM device of FIG. 1. The present bit-linestructure is merely an illustration, and should not limited the claimsas defined herein. The cross-sectional view diagram 200 includes theP-type well region 22 and the gate electrode 54 (or word line). Abit-line 204 is formed in a trench 201, having sides and a bottom. Thistrench has an insulating layer, including a bottom insulating layerportion 203 and a side insulating layer portion 202, overlying itsperiphery. This insulating layer isolates the bit-line from the P-typewell region 22. As shown, the bit-line is formed perpendicular to theword line(s) 54, and provides a connection to each of the transistorsource/drain regions adjacent to the bit-line.

[0029] In particular, the bit-line connects to the source/drainregion(s) 46 of the field effect transistor(s) 18. This connectionoccurs through a contact opening 207 in the side insulating layerportion 202. That is, a portion of the side insulating layer is removedbefore bit-line formation and forms the contact opening used forcontacting the source/drain region(s) 46 to the bit-line 204. Using a0.25 μm design rule, the contact opening width ranges from about 2,000to about 2,800 Å, and is preferably about 2,200 Å. A depth of suchcontact opening ranges from about 2,200 to about 2,800 Å, and ispreferably about 2,500 Å.

[0030] The bit-line is made of a conductive material. Preferably, thebit-line is a polysilicon layer in-situ doped with N-type impurities,e.g., phosphorous, etc. Alternatively, the bit-line can be made bydepositing the polysilicon layer and heavily doping with POCl₃ diffusionor ion implantation with annealing. The bitline is confined in thetrench width and trench depth. Corresponding to the bit-line thicknessis a trench depth, which has about a 1,000 Å top insulating portion andabout a 500 Å bottom insulating portion. Of course, the bit-line alsomay be made of other materials such as polycide or combination ofmaterials using different dimensions.

[0031] Overlying the bit-line is a top insulating layer portion 205.This top insulating portion 205 isolates the bit-line from overlyingdevice elements such as the gate electrode and others. Preferably, theinsulating layer portions, including the top insulating layer portion205, the side insulating layers portion 202, and bottom insulating layerportion 203, are defined around the periphery of the bit-line togenerally isolate it from the P-type well region and other deviceelements, defined around the trench periphery. As shown, the topinsulating layer 205 connects to the side insulating layer portions 202,which connect to the bottom insulating layer 203 portion.

[0032]FIG. 3 is an alternative cross-sectional view diagram 300 of thebitline structure of FIG. 2. This cross-sectional view diagramillustrates the connection between the bit-line 204 and the source/drainregion 46 through the contact opening 207. As shown, the opening 207allows the bit-line 204 to connect to the N+ type source/drain region50. This N+ type source/drain region provides lower resistance than itsadjacent N− type LDD region, and therefore facilitates the transfer ofcharge representing a signal from the source/drain region 46 of thememory cell to the bit-line 204. Preferably, the connection between thebit-line 204 and source/drain region 46 occurs at this N+ typesource/drain region 50.

[0033] Adjacent to the contact opening 207 is the top insulating layerportion 205 and the side insulating layer portion 202A. This topinsulating layer portion 205 and side insulating layer portion 202A areconnected to the side insulating layer portion 202 and the bottominsulating layer portion, respectively, which are connected to eachother. This combination of insulating layer portions isolates thebit-line 204 from adjacent device elements, but connects the bit-line tothe transistor source/drain region 46. Each DRAM memory cell has such abit-line connection.

[0034]FIG. 4 is a simplified top-view diagram 400 of the present DRAMintegrated circuit structure. This top-view diagram is merely anillustration, and should not limit the claims as defined herein. Thetop-view diagram is defined as an array having a y-direction and anx-direction. Gate electrodes 54 run in the x-direction, and are definedoverlying the P-type well regions 26. Each lower capacitor electrode 26,defined lengthwise in the y-direction, is formed over the gate electrode54. A plurality of bit-lines 204 run underlying the gate electrodes 54in the y-direction, and perpendicular to the gate electrodes 54. Eachbit-line includes a plurality of contacts 207, connecting the bit lineto its respective source/drain region of the field effect transistor.

II. Dram Fabrication Techniques

[0035] An overall fabrication method according to the present inventionmay be briefly outlined as follows.

[0036] (1) Provide a semiconductor substrate.

[0037] (2) Mask 1: Form P-type wells within the semiconductor substrate.

[0038] (3) Mask 2: Form N-type wells within the semiconductor substrate.

[0039] (4) Form protective layer comprising a pad oxide layer and asilicon nitride layer.

[0040] (5) Mask 3: Pattern active area to define trench regions.

[0041] (6) Form trench regions.

[0042] (7) Form trench sidewall and bottom oxidation.

[0043] (8) Mask 4: Define bit-line contact, and strip photoresist.

[0044] (9) Deposit in-situ doped polysilicon to fill trench regions.

[0045] (10) Etch back in-situ doped polysilicon maintaining in-situdoped polysilicon within the trench.

[0046] (11) Mask 5: Define non-bit-line trench regions, and removein-situ doped polysilicon in the non-bit-line trench regions.

[0047] (12) Oxidize in-situ doped polysilicon in bit-line trenchregions.

[0048] (13) Mask 6: Mask P-type channel regions and implant channel stopregions up to the trench bottoms.

[0049] (14) Deposit borophosphosilicate glass (BPSG) to fill the trenchregions in the non-bit-line trench regions.

[0050] (15) Remove the protective layer from the active regions.

[0051] (16) Perform blanket threshold implant.

[0052] (17) Mask 7: Mask N-type well regions and implant P-typeimpurities into the memory cell regions (or P-type well regions) toadjustment threshold voltage.

[0053] (18) Form gate oxide layer.

[0054] (19) Form doped gate polysilicon layer or polycide (or poly-1).

[0055] (20) Mask 8: Define gate polysilicon layer to form gateelectrodes.

[0056] (21) Mask 9: Define N− type lightly doped drain (LDD) regions andimplant N− type impurities.

[0057] (22) Mask 10: Define P− type LDD region and implant P− typeimpurities.

[0058] (23) Form sidewall spacers on sides of the polysilicon gateelectrodes.

[0059] (24) Mask 11: Define N+ type source/drain regions and implant N+type impurities.

[0060] (25) Mask 12: Define P+ type source/drain regions and implant P+type impurities.

[0061] (26) Mask 12: Define capacitor regions covering bit-line regionsand word-line regions with photoresist.

[0062] (27) Remove BPSG in the trench capacitor regions, and stripphotoresist.

[0063] (28) Deposit inter polysilicon oxide layer.

[0064] (29) Mask 14: Define capacitor cell contact regions and etch.

[0065] (30) Deposit poly-2 layer and dope.

[0066] (31) Mask 15: Define poly-2 layer to correspond to a lowercapacitor electrode.

[0067] (32) Form cell capacitor dielectric.

[0068] (33) Deposit poly-3 layer and dope (or in-situ doped poly-3deposition).

[0069] (34) Mask 16: Define poly-3 layer to correspond to an uppercapacitor electrode.

[0070] (35) Deposit BPSG/NSG (non-doped silicate glass) layers, andflow.

[0071] (36) Mask 17: Define contact pattern in the BPSG/NSG layers.

[0072] (37) Sputter first metal layer.

[0073] (38) Mask 18: Define first metal layer.

[0074] (39) Deposit inter-metal oxide.

[0075] (40) Mask 19: Define via pattern.

[0076] (41) Sputter second metal layer.

[0077] (42) Mask 20: Define second metal layer.

[0078] (43) Deposit passivation layer and polymide coating.

[0079] (44) Mask 21: Define pad regions and fuse opening regions.

[0080] (45) Polymide cure.

[0081] (46) Etch passivation layer to define pads.

[0082] (47) Sintering.

[0083] These steps provide an improved capacitor having a shallow trenchand stack capacitor plate. Each of these capacitor plates is defined inthe trench and over portions of the gate electrode of the field effecttransistor. Accordingly, a larger capacitor surface area is achieved,thereby improving storage capacity. A bit-line structure defined in atrench also is provided. This bit-line structure connects to respectivesource/drain regions, without employing the complex topography of theconventional techniques. These steps are also merely illustrative, andshould not limited the scope of the claims. Details of the presentmethod are described by way of the FIGS. below.

[0084] FIGS. 5-14 illustrates a simplified fabrication method of a DRAMintegrated circuit device, according to the present invention. Thepresent method is merely an illustration, and should not limit the scopeof the claims herein. The method begins by providing a semiconductorsubstrate 11, as illustrated by FIG. 5. The substrate can be anysuitable wafer for the fabrication of the present integrated circuitdevice. This wafer undertakes, for example, complementary metal oxidesemiconductor (CMOS) device fabrication techniques for DRAM devices.Other fabrication techniques also can be used depending upon theparticular application.

[0085] A photoresist mask is defined overlying a top surface of thesemiconductor substrate to form P-type well regions 22. These P-typewell regions 22 are formed by implanting impurities comprising P-typematerials into the substrate. P-type impurities include boron or thelike. The photoresist mask is stripped by conventional techniques.N-type channel devices now can be formed in the P-type well regions.

[0086] N-type wells also are defined within the semiconductor substrate.In particular, a photoresist mask is formed overlying the P-type wellregions of the semiconductor substrate. An implanting step forms theN-type well regions in the semiconductor substrate. N-type impuritiescomprise materials such as phosphorous, arsenic, and others. Thephotoresist mask is stripped by conventional techniques. P-type channeldevices now can be formed in the N-type well regions.

[0087] A combination of dielectric layers 501 is defined overlying thesubstrate to form a protective layer, as illustrated by FIG. 5. That is,the protective layer is used as a masking layer. This protective layercomprises a pad oxide layer 503 and an overlying silicon nitride layer505. The pad oxide layer is 200 to 300 Å thick. The silicon nitridelayer is 1,200 to 1,800 Å thick. Optionally, the silicon nitride layer505 includes another overlying silicon dioxide layer (not shown). Theselayers are patterned to define a plurality of trench regions, includinga capacitor trench 20 and a bit-line trench 201, as illustrated by FIG.6.

[0088] A dry etching technique is used to form the capacitor trench 20and the bit-line trench 201. An example of this dry etching techniquecan include reactive ion etching, plasma etching, or the like.Preferably, the trench is relatively shallow compared to thoseconventional deep trenches for capacitors, and is therefore easier tofabricate consistently. Using a 0.25 μm design rule, the capacitortrench depth ranges from about 0.8 to about 1.2 μm, and is preferablyabout 1.0 μm. The trench also includes a 0.4 μm width. Using the samedesign rule, the bit-line trench depth can be similar to the capacitortrench and ranges from about 0.8 to about 1.2 μm, and is preferablyabout 1.0 μm. This trench also is 0.25 μm wide. Of course, the depth andwidth of each trench depend upon the application.

[0089] A layer of dielectric isolation material is defined in each ofthe trenches, including the capacitor trench 20 and the bit-line trench201, as illustrated by FIG. 7. In particular, the capacitor trench 20includes a dielectric layer 24 overlying the trench bottom 32 and trenchsides 34. The bit-line trench 201 has a side dielectric layer portion202 and a bottom dielectric layer portion 203, overlying the trenchsides and bottom, respectively. These trenches are preferably coveredwith an oxidation layer via thermal oxidation of silicon. This oxidationlayer has a sufficient thickness to isolate its overlying structure fromthe substrate and other device elements. Preferably, the oxidation layerincludes a thickness ranging from about 400 to about 600 Å, and ispreferably about 500 Å. The trench also may be coated with an oxidelayer or multiple dielectric layers, deposited by chemical vapordeposition (CVD) or other suitable techniques. Of course, the dielectricmaterial(s) and its thickness depend upon the application.

[0090] Masking and etching techniques are used to define bit-linecontacts in the dielectric layer formed in the bit-line trenches. Thesebit-line contacts are defined as openings 207 in the dielectric layer,overlying the trench sides. In an embodiment using an oxide dielectriclayer, openings are made by coating the top surface of the substrate,including trenches, with a photoresist layer. Coating is followed bysteps of patterning the photoresist to form exposed regions overlyingcontacts, and wet etching the exposed regions to form the bit-linecontact openings. Each of these bit-line contact openings is 0.25 μmwide, and is 3,000 Å deep. The photoresist is then stripped usingconventional techniques. During later process steps, the contact openingprovides a via structure to connect the bit-line to a source/drainregion of each respective field effect transistor.

[0091] These trenches are now filled using an in-situ doped polysiliconfill layer 801, as illustrated by FIG. 8. The in-situ doped polysiliconlayer is heavily doped to provide a selected conductivity. This dopingis preferably N-type, using phosphorus for example, and is at aconcentration ranging from about 2×10²⁰ to about 6×10²⁰ atoms/cm³, andis preferably 4×10²⁰ atoms/cm³. In the bit-line trench, the dopedpolysilicon layer fills the contact opening and forms overlying againstthe surface of the substrate. This substrate surface will correspond toa source/drain region of the field effect transistor.

[0092] An etching step removes an upper portion of the in-situ dopedpolysilicon layer. This etching step also removes some of the in-situdoped polysilicon layer in the trenches. Preferably, the top surface ofthe polysilicon is about 1,000 Å from the top surface of the siliconsubstrate. Examples of this etching step include plasma etching,reactive ion etching, and others.

[0093] The in-situ doped polysilicon is removed from non-bit-line-trenchareas. That is, the in-situ doped polysilicon is removed from thecapacitor trenches, but not the bit-line trenches. In an embodiment,this removal of the doped polysilicon occurs by coating the top surfaceof the substrate with photoresist and exposing regions overlying thecapacitor trenches. A subsequent etching step removes the dopedpolysilicon layer from these capacitor trenches.

[0094] Upon removing the in-situ doped polysilicon, each capacitortrench is now open, leaving its insulating layer intact. The capacitortrench is filled using a filler material. This filler material should beeasy to apply, provide good masking characteristics, and can beselectively removed during a later processing step. In one embodiment,BPSG 901 fills these trenches, as illustrated by FIG. 9. Of course,other materials also can be used depending upon the application.

[0095] An upper portion 205 of the in-situ doped polysilicon in thebit-line trench is oxidized via thermal treatment, also illustrated byFIG. 9. This polysilicon layer is exposed to high temperature and anoxidizing compound, e.g., oxygen, water, etc. Thermal treatment of thein-situ doped layer converts the polysilicon into a silicon dioxidelayer having insulating qualities. This silicon dioxide layer includes athickness ranging from about 400 to about 600 Å, and is preferably about500 Å. This thickness must be sufficient to isolate the bit-line fromits overlying device elements. Of course, other techniques (e.g., CVD,etc.) also may be used to form this silicon dioxide layer.

[0096] Channel stop regions are then formed in the substrate. In oneembodiment, steps of masking P-type channel regions and implantingchannel stop regions are performed. Preferably, implanting occurs to adepth corresponding to the trench bottoms. The channel stop implant usesan N-type implant, e.g., phosphorous, etc.

[0097] The protective layer is removed from the active regions, asfurther illustrated by FIG. 9. This protective layer comprises silicondioxide and silicon nitride. The silicon nitride layer can be removedusing a dry etching technique or wet etching, e.g., phosphoric acid,etc. The silicon dioxide layer overlying the substrate must beselectively removed, thereby preventing damage to the substrate. In oneembodiment, the silicon dioxide is selectively removed using a solutionof hydrofluoric acid or the like. Of course, other techniques may beused depending upon the application.

[0098] N-type channel MOS devices and P-type channel PMOS devices,typifying the CMOS process, will be formed onto the P-type well regionsand N-type well regions, respectively. DRAM memory cells are definedinto the P-type well regions. Fabrication of these devices occurs usingthese following steps.

[0099] An implanting step introduces a threshold implant overlying theentire surface of the substrate. This implant blanketly introducesN-type impurities overlying both the P-type and the N-type well regions.In one embodiment, the N-type impurities comprise phosphorous, arsenic,or the like.

[0100] A photoresist mask is defined overlying N-type well regions forimplanting P-type impurities, e.g., boron, etc. This P-type implantingstep sets the threshold voltage of the N-type channel devices in each ofthe memory cells. The implant depends upon gate oxide thickness.Alternatively, P-type impurities are implanted before N-type impurities.

[0101] A gate oxide layer 52 is formed overlying the top surface of theP-type well regions, as illustrated by FIG. 10. This gate oxide layer isa high quality oxide, and is also typically thin to promote forefficient switching of the device. The thickness of such a gate oxidelayer typically ranges from about 90 Å to about 110 Å, and is preferablyabout 100 Å.

[0102] A deposition step forms a polysilicon layer overlying the oxidelayer. The polysilicon layer or polycide (WSi_(x) on top of poly) rangesfrom about 2,500 to about 3,500 Å thick, and is preferably about 3,000 Åthick. The polysilicon layer is also typically doped with an N-typeimpurity at a concentration of from about 4×10²⁰ to 6×10²⁰ atoms/cm³,and preferably at about 5×10²⁰ atoms/cm³. A step of implanting andannealing provides the N-type impurities into the polysilicon layer.Alternatively, the N-type impurities are diffused or formed in-situ withthe polysilicon layer to reduce the number of processing steps for thepolycide gate embodiment, a thinner poly around 1,500 Å is applied anddoped followed by about 1,000 Å WSi_(x) deposition.

[0103] Patterning the polysilicon layer or polycide defines thepolysilicon gate electrodes 54, as illustrated by FIG. 10. These gateelectrodes, termed as word lines, are often formed by any suitableseries of photolithographic steps including masking, developing,etching, and others. Each gate electrode includes edges havingsubstantially vertical features, but may also have features that are notsubstantially vertical. The exact geometry for each gate electrode willdepend upon the application.

[0104] Using each gate electrode as a mask, a blanket implant processintroduces N− type impurities into a portion of the wells to define theN− type LDD regions 42, 48 in the P-type wells 22. The N-type impuritydosage ranges from about 1×10¹³ to about 5×10¹³ atoms/cm², and ispreferably at about 3×10¹³ atoms/cm². The angle at which the implanttakes place ranges from angles greater than about 0 degree, and ispreferably about 30 degrees to about 45 degrees from a lineperpendicular to the channel direction. Alternatively, N-type wellregions are masked and N-type implants are made into the P-type wellregions, defining the N-type LDD regions. This sequence of steps definesthe N-type LDD region in the memory cells.

[0105] P-type well regions are masked and P− type impurities areintroduced into the N-type well regions. These implants define the P−type LDD regions in the N-type well regions. P− type LDD regions includea dosage ranging from about 1×10³ to about 5×10¹³ atoms/cm², and arepreferably at about 3×10¹³ atoms/cm². The P− type LDD regions may alsobe angle implanted depending upon the application.

[0106] Sidewall spacers 56 are defined on edges of each polysilicon gateelectrode 54. The sidewall spacers 56 are typically formed by the stepsof depositing a layer of dielectric material, densifying such layer, andremoving horizontal surfaces of such layer. This layer is made of amaterial such as a silicon dioxide, a silicon nitride, combinationsthereof, and the like. The step of densifying such dielectric materialseals the polysilicon gate electrode 54 from overlying layers, e.g., adielectric material such as silicon dioxide, silicon nitride,combinations thereof, and the like. Anisotropic etching performed on thedensified dielectric layer removes horizontal surfaces of such layer,forming the sidewall spacers. The anisotropic etching step removes thehorizontal surfaces of the dielectric material and leaves the sidewallspacers remaining intact. This anisotropic etching step includestechniques such as reactive ion etching, plasma etching, and others.

[0107] Masking and implanting steps define source/drain regions for eachMOS device. In particular, a photoresist mask is used to protect regionsdefining P− type channel devices, thereby exposing source/drain regionsfor the N-type channel devices. Implanting N+ type impurities into theseexposed regions defines the N+ type source/drain regions 40, 50, as alsoillustrated by FIG. 10. These impurities include phosphorous and thelike. The dosage of the N+ type impurities ranges from about 3×10¹⁵atoms/cm² to about 5×10¹⁵ atoms/cm², and is preferably about 4×10¹⁵atoms/cm². The angle at which the implant takes place ranges from about0 degrees to about 7 degrees, and is preferably at about 0 degrees froma line perpendicular to the channel direction. The photoresist mask isstripped by conventional techniques.

[0108] Another photoresist mask now protects the N-type channel devices,and exposes the source/drain regions for the P-type channel devices. P+type impurities are introduced into the source/drain regions of theP-type channel devices. The dosage of the P+ type impurities ranges fromabout 3×10¹⁵ to about 5×10⁵ atoms/cm², and is preferably about 4×10¹⁵atoms/cm². The photoresist mask is then stripped using conventionaltechniques.

[0109] The top surface of the substrate is then masked to defineopenings over the trench capacitor regions. That is, a photoresist maskcovers the bit-line and the word line. The BPSG 901 is removed from thetrench capacitor regions. In one embodiment, a wet etching step usinghydrofluoric acid selectively removes the BPSG layer from the trench,leaving the insulating regions 24 remaining intact. Alternatively, dryetching techniques may be used to selectively remove the BPSG layer fromthe trench. The photoresist mask is stripped using conventionaltechniques.

[0110] A CVD process forms an inter-layer dielectric 60 overlying thegate electrodes 54, as illustrated by FIG. 11. This inter-layerdielectric can be a suitable material comprising TEOS and others. Atechnique such as APCVD, PECVD, LPCVD, and the like deposits theinter-layer dielectric, e.g., silicon dioxide, etc. Of course, thetechnique used depends upon the application.

[0111] A step of providing a photoresist mask overlying top surfaceregions of the substrate, including the capacitor trench, to formexposed regions overlying cell contact regions 36 is performed. Thesecell contact regions or openings in the isolation regions are defined byetching techniques, as illustrated in FIG. 11. Examples of these etchingtechniques include plasma etching, reactive ion etching, and others.Alternatively, a wet etching technique using a selective etchant such ashydrofluoric acid may be used. As shown, each opening is provided toconnect the lower capacitor electrode to the field effect transistorsource/drain region. The opening is about 2,000 Å lower than the surfaceof the substrate. The top portion of the exposed source/drain regions issubstantially free from oxidation before the next process step. A diluteacid dip or dry etching technique may be used to clear the source/drainregions.

[0112] This next step deposits a lower capacitor electrode layeroverlying the isolation regions and an exposed portion 36 of thesource/drain region. The lower capacitor layer also is provided over atop portion 1201 of the inter-layer dielectric 60, thereby furtherincreasing the surface area of the capacitor cell. This increasedsurface area provides an increase in capacitance. Preferably, the lowercapacitor layer is made of polysilicon, which is heavily doped withimpurities for reducing resistance. The impurities are introduced usingmultiple angle implanting techniques or can be in-situ-doped, dependingupon the application. In one embodiment, the impurities are N-type,e.g., phosphorous, etc.

[0113] Step of masking and etching define the lower capacitor layer intoa lower capacitor electrode plate 26, as illustrated by FIG. 12. Thislower capacitor electrode plate connects to the field effect transistorsource/drain region 38 through the contact opening 36. The photoresistlayer is then stripped using conventional techniques. Before fabricationof an overlying dielectric layer, the lower capacitor layer is clearedusing dry etching techniques or the like.

[0114] A capacitor dielectric layer(s) 28 is formed overlying the lowercapacitor plate. This capacitor dielectric layer is used to store chargebetween the lower capacitor plate and an upper capacitor plate. In oneembodiment, the capacitor dielectric layer is a high qualitynitride/oxide composite layer. In a preferred embodiment, the capacitordielectric layer comprises a silicon dioxide layer overlying the lowercapacitor plate, a silicon nitride layer overlying the silicon nitridelayer, and another silicon dioxide layer overlying the nitride layer.This combination of layers provides for high storage capacitycharacteristics and ease in fabrication.

[0115] In completing the capacitor structure, an upper capacitor layeris deposited overlying the capacitor dielectric layer. This uppercapacitor layer can be a heavily doped polysilicon layer for reducingresistance. The polysilicon layer can be doped using multiple angleimplanting techniques or can be in-situ doped, depending upon theapplication. Steps of masking and etching define the upper capacitorlayer into an upper capacitor plate, as illustrated by FIG. 13. Thelower capacitor plate, the capacitor dielectric layer, and the uppercapacitor plate define the capacitor structure. As shown, a portion ofthe capacitor structure lies over the field effect transistor as well asthe trench to increase capacitor surface area, thereby providing greatercapacitance.

[0116] Thick layers 14 of BPSG/NSG deposit overlying the top surface ofthe entire substrate, as illustrated by FIG. 14. Typical CVD techniquesdeposit the combination of BPSG/NSG layers. These BPSG/NSG layersisolate the lower device structures from upper metallization. TheBPSG/NGS layers are flowed using an annealing step. A surface of theselayers is masked with photoresist to define contact openings. An etchingprocess forms these contact openings. The photoresist is then strippedusing conventional techniques.

[0117] A first metal layer is formed overlying these layers and isformed in the contact openings to provide electrical connections. Aprocess of masking and etching patterns the first metal layer 16, asillustrated by FIG. 14. An inter-metal oxide layer 17 is depositedoverlying the patterned first metal layer 16. Typical CVD techniquesdeposit this inter-metal oxide layer.

[0118] A via pattern is defined in the inter-metal oxide layer usingconventional photoresist and etching techniques. This via patternprovides openings used for electrical contacts between the first metallayer and the second metal layer. This second metal layer is sputteredoverlying the inter-metal oxide and is sputtered into the vias. A stepof patterning defines the second metal layer.

[0119] Remaining fabrication steps include deposition of a passivationlayer, including a silicon nitride layer and a silicon dioxide layer.This passivation layer is patterned to form openings for bonding padregions and fuse openings. The openings are made by etching techniques.The entire surface is then coated with polymide. A final masking andetching step patterns this coated surface. After patterning, the coatedsurface is cured. Further process steps include wafer sort, assembly,testing, and others.

[0120] While the above is a full description of the specificembodiments, various modifications, alternative constructions andequivalents may be used. For example, while the description above is interms of a DRAM structure, it would be possible to implement the presentinvention with SRAM, or the like.

[0121] Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A memory device, said device comprising: asemiconductor substrate comprising a recessed region, said recessedregion having sides extending from a bottom surface; a field effecttransistor, said field effect transistor including a source/drain regionadjacent to said recessed region; an insulating layer overlying therecessed region; a lower capacitor plate overlying said insulating layerand over a portion of said field effect transistor, said lower capacitorplate being connected to said source drain region; a capacitordielectric overlying said lower capacitor plate; and an upper capacitorplate overlying said dielectric layer.
 2. Device of claim 1 wherein saidrecessed region is provided with a depth ranging from about 8,000 toabout 12,000 Å.
 3. Device of claim 1 wherein said lower capacitor plateis provided with a thickness ranging from about 1,000 to about 1,400 Å.4. Device of claim 1 wherein said lower capacitor plate is provided witha thickness of less than about 1,200 Å.
 5. Device of claim 1 whereinsaid lower capacitor plate is an in-situ doped polysilicon layer. 6.Device of claim 1 wherein said upper capacitor plate is an in-situ dopedpolysilicon layer.
 7. Device of claim 1 wherein said capacitordielectric comprises an oxide layer.
 8. Device of claim 1 wherein saidcapacitor dielectric comprises an oxide layer and a nitride layer. 9.Device of claim 1 wherein said field effect transistor is an MOStransistor.
 10. A method of forming a capacitor structure for a memorydevice, said method comprising: providing a semiconductor substrate;forming a recessed region, said recessed region having sides extendingfrom a bottom surface; forming an insulating layer defined overlyingsaid recessed region; forming a source/drain region adjacent to saidrecessed region; forming a lower capacitor plate overlying saidinsulating layer and over a portion of said field effect transistor,said lower capacitor plate being connected to said source/drain region;forming a capacitor dielectric overlying said lower capacitor plate; andforming an upper capacitor plate overlying said dielectric layer. 11.The method of claim 10 wherein said recessed region is provided with adepth ranging from about 8,000 to about 12,000 Å.
 12. The method ofclaim 10 wherein said lower capacitor plate is provided with a thicknessranging from about 1,000 to about 1,400 Å.
 13. The method of claim 10wherein said lower capacitor plate is provided with a thickness of lessthan about 1,200 Å.
 14. The method of claim 10 wherein said lowercapacitor plate is an in-situ doped polysilicon layer.
 15. The method ofclaim 10 wherein said upper capacitor plate is an in-situ dopedpolysilicon layer.
 16. The method of claim 10 wherein said capacitordielectric comprises an oxide layer.
 17. The method of claim 10 whereinsaid capacitor dielectric comprises an oxide layer and a nitride layer.18. The method of claim 10 wherein said field effect transistor is anMOS transistor.
 19. A dynamic random access memory integrated circuit,said integrated circuit element comprising: a semiconductor substratecomprising a recessed region, said recessed region having sidesextending from a bottom surface; a field effect transistor, said fieldeffect transistor including a source/drain region adjacent to saidrecessed region; and an insulating layer defined overlying said recessedregion; a conductor defined within said recessed region, said conductorbeing connected to said source drain region.
 20. A method of formingbit-line in a dynamic random access memory integrated circuit element,said method comprising: providing a semiconductor substrate; forming arecessed region in said semiconductor substrate, said recessed regionhaving sides extending from a bottom surface; forming an insulatinglayer defined overlying said recessed region; forming a field effecttransistor, said field effect transistor including a source/drain regionadjacent to said recessed region; and forming a conductor defined withinsaid recessed region, said conductor being connected to said sourcedrain region.